1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Background Art
When a next-generation CMOS (complementary metal oxide semiconductor) device, which may have a gate length on the order of submicrons, is manufactured, it is highly possible that the gate electrodes of MIS transistors constituting the device cannot be formed of silicon, the material used in previous generation devices.
One reason for this is the sheet resistance of silicon, which is as high as a few tens Ω/square. When silicon is used to form a gate electrode, a so-called RC delay cannot be ignored when the device is operated. Generally, the sheet resistance of a gate electrode having a gate length of a submicron size for which the RC delay can be ignored is considered to be 5 Ω/square or less.
Another reason is the depletion in the gate electrode. Since the solubility limit of an impurity (dopant) with respect to silicon is about 1×1020 cm−3, when a gate electrode is formed of silicon, a depletion layer having a limited length extends in the gate electrode, which causes the deterioration of the current drivability of the MIS transistor.
Specifically, the depletion layer functions as a capacitance between the gate electrode and a channel region, the capacitance being connected in series to a gate insulating film. Accordingly, the gate capacitance of the MIS transistor substantially corresponds to the sum of the capacitance of the gate insulating film and the capacitance of the depletion layer. When recalculated as, for example, the thickness of silicon oxide constituting the gate insulating film, the capacitance of the depletion layer corresponds to a silicon oxide layer having a thickness of about 0.3 nm-0.5 nm. This causes a problem in that the current drivability of transistor elements is decreased.
Since the standard gate length of an MIS transistor will become on the order of submicrons in the future, the thickness of a gate insulating film thereof is expected to become 1.5 nm or less when calculated as a silicon oxide. This would make the capacitance caused by the depletion layer 20% or more of the capacitance of the gate insulating film. Such a high ratio cannot be ignored.
One way to solve the aforementioned problem is to add a high-concentration impurity (phosphorous, boron, etc.) to the silicon gate electrode to decrease the specific resistance thereof. However, as already mentioned, in an MIS transistor having a gate length of submicron size, the thickness of the gate insulating film is 1.5 nm or less. In such a case, a problem arises in that the impurity in the gate electrode passes through the gate insulating film, and diffuses into or penetrates the silicon substrate.
Such diffusion or penetration of an impurity may cause a decrease in current drivability of MIS transistor or a variation in threshold voltage.
In an attempt to solve this problem, recently, a high melting point metal such as molybdenum, tungsten, tantalum, etc. or a nitride thereof is used to form a gate electrode. This is referred to as a metal gate technique.
According to the metal gate technique, a gate electrode is formed of a metal having a specific resistance smaller than that of silicon. Therefore, basically the RC delay thereof can be ignored. Furthermore, in principle, no depletion layer is generated in a metal. Accordingly, no decrease in current drivability of an MIS transistor, as in the case of a silicon gate, is caused by the depletion layer when a metal is used. Moreover, since it is not necessary to add an impurity to a metal gate in order to decrease the resistance, no decrease in current drivability or variation in the threshold voltage in a MIS transistor is caused by diffusion or penetration of an impurity.
However, the metal gate technique is not perfect. When a CMOS device is formed using the metal gate technique, the following specific problem arises.
In the metal gate technique, a metal material having a work function close to that of p+ silicon should be used to form the gate electrode of a p-channel MIS transistor, and a metal material having a work function close to that of n+ silicon should be used to form the gate electrode of an n-channel MIS transistor. In this manner, it is possible to set the threshold voltage of the p-channel MIS transistor and the n-channel MIS transistor at appropriate values.
This is the so-called dual φ (phi) metal gate technique. Actually, however, it is difficult to find a metal material having a work function similar to that of p+ silicon or n+ silicon and having a heat-resistant property. Accordingly, no optimum material meeting the aforementioned conditions to form a gate insulating film or a gate electrode has been found as of today.
If a heat-resistant metal material having an appropriate work function suitable for forming a gate insulating film and a gate electrode were found, such a metal material would not be useful if such a metal material could not be used to form a gate insulating film and a gate electrode by an LSI manufacturing process. For example, in a silicon gate electrode formed by a conventional self-aligning process, a p-channel MIS transistor and an n-channel MIS transistor are simultaneously processed and formed, thereby simplifying the steps of the process. However, since different metal materials are used to form a p-channel MIS transistor and an n-channel MIS transistor in the dual φ metal gate technique, it is not possible to perform simultaneous processing. Accordingly, an increase in the number of steps in the process becomes a problem. At the same time, there is a problem in that optimum processing conditions should be considered for each material.
There is a technique in that work function is changed by implanting impurity atoms such as nitrogen atoms (R. Lin et al., “An Adjustable Work Function Technology Using Mo Gate for CMOS Devices”, IEEE Electron Device Letters, vol. 23, pp.49-51 (2004) (Reference 1), and T. Aoyama and Y. Nara, “Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO2 High-k Gate Dielectrics”, Jap. J. Appl. Phys., vol.44, pp. 2,283-2,287 (2005) (Reference 2)) or oxygen or fluorine atoms (Japanese Patent Laid-Open Publication No. 2003-273350 (Reference 3)) into either of the gate electrode of an n-channel MIS transistor or the gate electrode of a p-channel MIS transistor. In this manner, it is possible to obtain a work function suitable for each transistor using the same metal gate electrode. This technique, which is referred to as single metal—dual φ technique, was expected to solve the aforementioned problem related to the complex manufacturing process.
However, in the conventional single metal—dual φ technique, there is a problem in that the variation in work function of gate electrode caused by the implantation of impurity atoms is not constant, making it difficult to control. In Reference 1 and Reference 2, nitrogen ions are implanted into Mo (molybdenum) in similar manners. However, the work function of Reference 1 is decreased by 0.42 eV, while the work function of Reference 2 is increased by 0.70 eV. Thus, the directions of the variation in work function are opposite to each other. According to Reference 1, the implantation of only a small amount of the impurity results in a great change in the work function of the metal since the electronegativity of the impurity is great. However, as can be understood from the case of the implantation of N (nitrogen) into Mo, the control of work function using this mechanism is very difficult, and the requirement of the accuracy of threshold voltage with respect to the finished transistor product cannot be met.